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d a t a sh eet preliminary speci?cation supersedes data of 2003 oct 06 2003 dec 16 integrated circuits tza3015hw 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit fibre optic transceiver
2003 dec 16 2 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw features general a-rabitte ? (1) : supports any bit rate from 30 mbit/s to 3.2 gbit/s with one single reference frequency 4-bit parallel interface selectable double data rate (ddr, half clock rate) or single data rate (sdr) clocking scheme on parallel interface, enabling easy interfacing with fpga devices i 2 c-bus and pin programmable six selectable reference frequency ranges transmitter, receiver and transceiver modes clean-up loop back mode line loop back mode diagnostic loop back mode serial loop timing mode single 3.3 v power supply. limiter limiting amplifier with typical 5 mv input sensitivity received signal strength indicator (rssi) loss of signal (los) indicator with adjustable threshold differential overvoltage protection. data and clock recovery and synthesizer supports any bit rate from 30 mbit/s to 3.2 gbit/s when using i 2 c-bus interface supports eight pre-programmed (pin selectable) bit rates: C sdh/sonet rates at 155.52 mbit/s, 622.08 mbit/s, 2488.32 mbit/s and 2666.06 mbit/s (stm16/oc48 + fec) C gigabit ethernet at 1250 mbit/s and 3125 mbit/s C fibre channel at 1062.5 mbit/s and 2125 mbit/s. provides stable clock signal at los frequency lock indicator for dcr loss of lock (lol) indicator for synthesizer itu-t compliant jitter tolerance for data and clock recovery (dcr) itu-t compliant jitter transfer for dcr in clean-up loop back mode itu-t compliant jitter generation for synthesizer. multiplexer 4 : 1 multiplexing ratio supports co-directional and contra-directional clocking 4-stage fifo for wide tolerance to clock skew rail-to-rail parallel inputs compliant with lvpecl, current-mode logic (cml) and lvds programmable parity checking cml data and clock outputs. demultiplexer 1 : 4 demultiplexing ratio adjustable lvds output swing frame detection for sdh/sonet and gigabit ethernet (ge) frames. i 2 c-bus con?gurable options programmable frequency resolution of 10 hz independent receive and transmit bit rate slice level adjustment to improve bit error rate (ber) six reference frequency ranges adjustable swing for cml serial data and clock outputs programmable polarity of rf i/os clock versus data swap for optimum connectivity swap of parallel bus for optimum connectivity mute function for a forced logic 0 output state programmable parity programmable 32-bit frame detection. (1) a-rate is a trademark of koninklijke philips electronics n.v.
2003 dec 16 3 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw applications any optical transmission system with line rates between 30 mbit/s and 3.2 gbit/s physical interface ic in receive and transmit channels transponder applications dense wavelength division multiplexing systems due to ddr clocking option, the ultimate physical interface for fpga based designs. general description the tza3015hw is a fully integrated optical network transceiver containing a limiter, data and clock recovery circuit, clock synthesizer, 1 : 4 demultiplexer and 4 : 1 multiplexer. the a-rate feature allows the ic to operate at any bit rate between 30 mbit/s and 3.2 gbit/s with one single reference frequency. all clock signals are generated using a fractional n synthesizer with 10 hz resolution offering a true continuous rate operating. for full configuration flexibility the transceiver can be programmed by pin and via the i 2 c-bus. ordering information type number package name description version tza3015hw htqfp100 plastic thermal enhanced thin quad ?at package; 100 leads; body 14 14 1 mm; exposed die pad sot638-1
2003 dec 16 4 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw block diagram dmx 1 : 4 61 62 59 60 57 58 55 56 52 53 parity generator and bus swap rxpd3/ rxpd3q 48 49 rxpar/ rxparq 88 clkdir 98, 99 rxprscl/ rxprsclq 41 lowswing rxpd2/ rxpd2q rxpd1/ rxpd1q rxpd0/ rxpd0q rxpc/ rxpcq 46 47 rxfp/ rxfpq 43 enba fifo 73 74 71 72 69 70 67 68 parity check and bus swap txpd3/ txpd3q 64 65 txpc/ txpcq txpd2/ txpd2q txpd1/ txpd1q txpd0/ txpd0q mux 4 : 1 76 77 txpar/ txparq mgu679 dlb mux lm mux phase detector vco loop mux loop mode select phase shift r 4 lpf frequency window detector tza3015hw clock synthesizer cref txprscl/ txprsclq crefq fref0 fref1 lol txpco/ txpcoq enddr interrupt controller int 30 inwindow winsize clean-up pll ipump 96 37 38 v cca 15, 18, 92 v cco 1, 34 v dd 25 v ee (1) v ccd (2) c c d d 16 17 ui cs(dr0) sda(dr1) scl(dr2) rxsdq 19 losth 21 los rxsd 5 6 txsdq txsd 9 10 3 txscq entxsc txsc 27 93 95 42 94 89, 90 91 79, 80 txparerr/ txparerrq clk mux 86, 87 pareven 81 overflow 82 45 enddr fiforeset 83 lm0 32 entx 31 enrx 28 lm1 29 lm2 los lim buf buf rssi i 2 c-bus 24 rref 14 23 22 13 20 rssi fig.1 block diagram. (1) connected to pins 2, 12, 26, 33, 35, 40, 50, 84 and 100. (2) connected to pins 4, 7, 8, 11, 36, 39, 44, 51, 54, 63, 66, 75, 78, 85 and 97.
2003 dec 16 5 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw pinning symbol pin description v ee die pad common ground plane v cco 1 supply voltage (clock generator) v ee 2 ground entxsc 3 enable serial clock v ccd 4 digital supply voltage txsd 5 serial data output txsdq 6 serial data output inverted v ccd 7 supply voltage (digital part) v ccd 8 supply voltage (digital part) txsc 9 serial clock output txscq 10 serial clock output inverted v ccd 11 supply voltage (digital part) v ee 12 ground ui 13 user interface select input rref 14 reference resistor input v cca 15 supply voltage (analog part) rxsd 16 serial data input rxsdq 17 serial data input inverted v cca 18 supply voltage (analog part) losth 19 loss of signal threshold input rssi 20 received signal strength indicator output los 21 loss of signal output cs(dr0) 22 chip select output (data rate select input 0) sda(dr1) 23 i 2 c-bus serial data input and output (data rate select input 1) scl(dr2) 24 i 2 c-bus serial clock input (data rate select input 2) v dd 25 supply voltage (digital) v ee 26 ground lm0 27 loop mode select input 0 lm1 28 loop mode select input 1 lm2 29 loop mode select input 2 int 30 interrupt output enrx 31 enable receiver entx 32 enable transmitter v ee 33 ground v cco 34 supply voltage (clock generator) v ee 35 ground v ccd 36 supply voltage (digital part) winsize 37 wide and narrow frequency detect window select input inwindow 38 frequency window detector output v ccd 39 supply voltage (digital part) v ee 40 ground lowswing 41 enable low lvds swing fref0 42 reference frequency select input 0 enba 43 enable byte alignment v ccd 44 supply voltage (digital part) enddr 45 enable ddr rxfp 46 frame pulse output rxfpq 47 frame pulse output inverted rxpar 48 parity output rxparq 49 parity output inverted v ee 50 ground v ccd 51 supply voltage (digital part) rxpc 52 parallel clock output rxpcq 53 parallel clock output inverted v ccd 54 digital supply voltage rxpd0 55 parallel data output 0 rxpd0q 56 parallel data output 0 inverted rxpd1 57 parallel data output 1 rxpd1q 58 parallel data output 1 inverted rxpd2 59 parallel data output 2 rxpd2q 60 parallel data output 2 inverted rxpd3 61 parallel data output 3 rxpd3q 62 parallel data output 3 inverted v ccd 63 supply voltage (digital part) txpc 64 parallel clock input txpcq 65 parallel clock input inverted v ccd 66 supply voltage (digital part) txpd0 67 parallel data input 0 txpd0q 68 parallel data input 0 inverted txpd1 69 parallel data input 1 txpd1q 70 parallel data input 1 inverted txpd2 71 parallel data input 2 txpd2q 72 parallel data input 2 inverted txpd3 73 parallel data input 3 txpd3q 74 parallel data input 3 inverted symbol pin description
2003 dec 16 6 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw v ccd 75 supply voltage (digital part) txpar 76 parity input txparq 77 parity input inverted v ccd 78 supply voltage (digital part) txpco 79 transmitter parallel clock output txpcoq 80 transmitter parallel clock output inverted pareven 81 parity select input (odd or even) overflow 82 fifo over?ow alarm output fiforeset 83 fifo reset input v ee 84 ground v ccd 85 supply voltage (digital part) txparerr 86 parity error output txparerrq 87 parity error output inverted clkdir 88 selection input between co- and contra-directional clocking symbol pin description txprscl 89 prescaler synthesizer output txprsclq 90 prescaler synthesizer output inverted lol 91 loss of lock output v cca 92 supply voltage (analog part) cref 93 reference clock input crefq 94 reference clock input inverted fref1 95 reference frequency select input 1 ipump 96 clean-up pll charge pump output v ccd 97 supply voltage (digital part) rxprscl 98 prescaler dcr output rxprsclq 99 prescaler dcr output inverted v ee 100 ground symbol pin description
2003 dec 16 7 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw handbook, full pagewidth 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 v dd scl(dr2) sda(dr1) cs(dr0) los rssi losth rxsdq rxsd v cca v cca rref ui v ee txscq txsc txsdq txsd v ccd v ccd v ccd v ccd entxsc v ee v cco v ccd rxpc rxpcq v ccd rxpd0 rxpd0q rxpd1 rxpd1q rxpd2 rxpd2q rxpd3 rxpd3q v ccd txpc txpcq v ccd txpd0 txpd0q txpd1 txpd1q txpd2 txpd2q txpd3 txpd3q v ccd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 v ee v ccd rxprsclq rxprscl ipump fref1 crefq cref v cca lol txprsclq txprscl clkdir txparerrq txparerr v ccd v ee fiforeset overflow pareven txpcoq txpco v ccd txparq txpar v ee lm0 lm1 lm2 int enrx entx v cco v ccd winsize inwindow v ccd v ee enddr v ee lowswing v ee v ee fref0 enba v ccd rxfp rxfpq rxpar rxparq 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 mgu680 tza3015hw fig.2 pin configuration.
2003 dec 16 8 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw functional description the tza3015hw contains the following main blocks: general part: configuration via i 2 c-bus mode or pre-programmed mode receiver part: limiting amplifier, data and clock recovery and demultiplexer transmitter part: clock synthesizer and multiplexer. general c onfiguration the ic features two types of user interface: i 2 c-bus or direct pin programming of eight predefined modes. the mode selection is set by pin ui. the i 2 c-bus mode is operational and a-rate functionality is enabled if pin ui is left open-circuit or connected to v cc (see table 1). if pin ui is connected to v ee , the eight pre-programmed modes can be selected with pins cs(dr0), sda(dr1) and scl(dr2). table 1 truth table for pin ui i 2 c- bus mode in i 2 c-bus mode the ic can be configured by using pins sda and scl. pin cs has to be high during the i 2 c-bus read or write actions. when pin cs is made low, the programmed configuration remains active, but signals sda and scl are ignored. in this way, all ics in the application with the same i 2 c-bus address (e.g. other tza3015hws) are individually accessible. the i 2 c-bus address is given in table 2. table 2 device address of the tza3015hw after power-up, the tza3015hw initiates a power-on reset (por) sequence to restore the default settings of the i 2 c-bus registers, regardless of the user interface. see table 21 for the defaults and a detailed list of all i 2 c-bus registers and the meaning of their contents. some functions of the tza3015hw can be controlled both using pre-program mode and via the i 2 c-bus. in these cases, an extra i 2 c-bus bit called i2c is available to set the programming precedence to pre-programmed or i 2 c-bus bit (default is selection by pre-programmed). p re - programmed mode the tza3015hw is primarily intended to be programmed via the i 2 c-bus. if no i 2 c-bus control is present in the application, the tza3015hw can be used in the pre-programmed mode (pin ui = low), with reduced functionality. the tza3015hw functions that are accessible in the pre-programmed mode and their associated pins are: all pre-programmed modes are supported by one single reference frequency the redefined pins dr0 to dr2 act as standard cmos inputs that select any of the desired data rates; see table 3 transceiver mode (transceiver, transmitter, receiver, off) (enrx and entx) enable serial clock output (entxsc) loss of signal threshold setting (losth) select loop mode (lm0 to lm2) automatic byte alignment for sdh/sonet or gigabit ethernet (enba) frame detection for sdh/sonet or gigabit ethernet even parity generation (pareven) in window detection (inwindow) sizeable frequency window: 1000 or 0 ppm (winsize) temperature alarm (int, open drain) co-directional or contra-directional clocking scheme (clkdir) enable ddr for both receiver and transmitter (enddr) cml serial rf outputs with typical 300 mv (p-p) single-ended signal (dc-coupled load) loss of lock detection (lol) fifo overflow indication (overflow) fifo reset (fiforeset) supported reference frequencies: 19.44, 38.88, 155.52 and 622.08 mhz. ui mode pin 22 pin 23 pin 24 low pre-programmed dr0 dr1 dr2 high i 2 c-bus cs sda scl device address bits r/ w a6 a5 a4 a3 a2 a1 a0 1010100x
2003 dec 16 9 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw table 3 truth table for pins dr2 to dr0 (pin ui = v ee ) receiver l imiting amplifier the tza3015hw contains a limiting amplifier (see fig.3). to achieve optimum receiver sensitivity for any bit rate, the bandwidth of the amplifier is automatically scaled with the bit rate. wideband noise of the optical front-end (photo detector and transimpedance amplifier) is thus reduced for lower bit rates. when using the i 2 c-bus, the bandwidth of the amplifier can be set independently of the bit rate with bits amp[2:0] in register limcon (d3h). the highest bandwidth is selected as default at power-up. received signal strength indicator (rssi) the signal strength at the input is measured with a logarithmic detector. the logarithmic detector converts the input signal amplitude into a voltage which can be measured at pin rssi. the rssi reading has a dynamic range of 40 db with a sensitivity (s rssi ) of 17 mv/db (typical) for a v i(p-p) range of 5 to 500 mv (see fig.4). v rssi can be calculated using the following formula: where: v rssi(32mv) = 680 mv (typical). dr2 dr1 dr0 protocol bit rate (mbit/s) low low low stm1/oc3 155.52 low low high stm4/oc12 622.08 low high low stm16/oc48 2488.32 low high high stm16 + fec 2666.06 high low low ge 1250.00 high low high 10ge 3125.00 high high low fibre channel 1062.50 high high high fibre channel 2125.00 handbook, halfpage mdb385 50 w in inq 50 w v ee v cca fig.3 limiter input termination configuration. v rssi v rssi(32mv) s rssi 20log v i(p-p) 32 mv ---------------- - + = handbook, full pagewidth mce412 0 5 0.3 0.6 0.68 0.9 1.2 v rssi (v) s rssi 10 32 10 2 10 3 500 300 v i(p-p) (mv) fig.4 v rssi as a function of v i(p-p) .
2003 dec 16 10 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw loss of signal (los) indicator besides the analog rssi output, a digital los indication is present on the tza3015hw. the rssi level is internally compared with a los threshold, which can be set by connecting an external resistor to pin losth or by means of an internal dac which is accessible via the i 2 c-bus. bit i2closth of register limloscon (d1h) enables the 8-bit dac, of which the value needs to be programmed into register limlosth (d0h). the threshold level is adjustable in 256 steps from 0 to 1.2 v. if the received signal strength is below the threshold value, pin los will be high. a default hysteresis of 3 db is applied in the comparator. the hysteresis can be set with bits htlc[2:0] in register limloscon (d1h). the programmable range is 0 to 7 db. the polarity of the los output can be inverted by bit lospol of register limloscon (d1h) to provide more flexibility in the application. losth reference setting by external resistor if the built-in dac is not used, the reference voltage level to pin losth can be set by connecting an external resistor (r2) between pin losth and ground. v losth is determined by the resistor ratio between r2 and r1 (see fig.5). for resistor r1 a value of 10 to 20 k w is recommended, yielding a current of 120 to 60 m a through r1. v losth = v ref represents a temperature stabilized and accurate reference voltage of 1.2 v. the minimum threshold level corresponds to 0 v and the maximum to 1.2 v. hence, the value of r2 may not be higher than r1. the accuracy of v losth depends mainly on the matching of the two external resistors. apart from using resistors (r1 and r2) to set the los threshold, an accurate external voltage source may also be used. if no resistor is connected or an external voltage higher than 2 / 3 v cc is applied to pin losth, the los detection circuit (including the rssi reading) is automatically switched off to reduce power dissipation. this auto power off function only works in the pre-programmed mode. i 2 c-bus mode allows flexible configuration. slice level adjustment due to asymmetrical noise in some optical transmission systems, a pre-detection signal-to-noise ratio improvement can be achieved by adding a dc offset to the input signal. this is done by the slice level circuit in the tza3015hw. the required offset depends on the photo detector characteristics in the optical front-end and the amplitude of the received signal. the slice level is adjustable between - 50 and +50 mv in 512 steps of 0.2 mv. bit slen of register limloscon (d1h) enables the slice function. the slice level is set by sign and magnitude convention. the polarity sign is set by bit slsgn in register limloscon (d1h). the magnitude is set by an 8-bit dac, accessible via register limsl (d2h), from 0 to 50 mv in 256 steps. the introduced offset is not present on input pins rxsd(q), in order not to affect the logarithmic rssi detector, which would detect the offset as a valid input signal. r2 r1 ------- v ref rssi los compare losth 1.2 v v ref rref los rssi mgu681 v cca v ee ground r2 r1 10 k w i fig.5 setting the losth reference level by external resistors.
2003 dec 16 11 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw d ata and c lock r ecovery (dcr) the tza3015hw recovers the clock and data contents from the incoming bit stream; see fig.6. the dcr uses a combined frequency and phase locking scheme, providing reliable and quick data acquisition on any bit rate between 30 mbit/s and 3.2 gbit/s. at power-up, coarse adjustment of the free running voltage controlled oscillator (vco) frequency is required. this is achieved by the frequency window detector (fwd) circuit. the fwd is a conventional frequency locked pll. the fwd checks the vco frequency, which has to be within a 1000 ppm window around the required frequency. the fwd then compares the divided vco frequency, also available on pins rxprscl(q), with the reference frequency on pins cref(q), usually 19.44 mhz. if the vco frequency is outside this window, the fwd disables the data phase detector (dpd) and forces the vco to a frequency within the window. as soon as the in window condition occurs, which is visible on pin inwindow, the dpd is enabled and will lock on the incoming bit stream. since the vco frequency is very close to the expected bit rate, the phase acquisition will be almost instantaneous, resulting in quick phase lock to the incoming data stream. although the vco is now locked to the incoming bit stream, the fwd is still supervising the vco frequency and takes over control if the vco frequency drifts outside the predefined frequency window. this might occur during a loss of signal situation. due to the fwd, the vco frequency is always close to the required bit rate, enabling rapid phase acquisition when the lost input signal returns. due to the loose coupling of 1000 ppm, the reference frequency does not need to be highly accurate or stable. any crystal-based oscillator that generates a reasonably accurate frequency (e.g. 100 ppm) will do. this only holds if the tza3015hw is used as a receiver since the synthesizer of the transmitter uses the same reference clock. the transmitter does need a very accurate reference frequency. fractional n synthesizer in the dcr the dcr section contains a fractional n synthesizer as frequency acquisition aid for the a-rate functionality. this allows the dcr to synchronize on incoming data, regardless of the received bit rate. any combination of bit rate and reference frequency is possible, due to the 22 bits fractional n synthesizer, allowing approximately 10 hz frequency resolution. the lsb (bit k0) should be set to logic 1 to avoid limit cycles (cycles of less than maximum length). this leaves 21 bits (bits k[21:1]), available for free programming. handbook, full pagewidth + data phase detector up recovered data from limiting amplifier and dlb mux divided cref(q) rxprscl(q) mgu683 recovered clock to demultiplexer prescaler buffer octave divider main divider n, k inwindow winsize reference divider ? m down frac ? n charge pump loop filter frequency window detector up down voltage controlled oscillator charge pump fig.6 functional diagram of data and clock recovery.
2003 dec 16 12 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw dcr programming programming the dcr involves four dividers: reference divider r main divider n fractional divider k octave divider m. the first step is to determine in which octave the desired bit rate fits, see fig.7 and tables 4 and 5. figure 7 shows the position of the most commonly used line rates in relation to the defined octaves of the tza3015hw. table 5 lists the most commonly used standards together with the associated line rates. table 4 clarifies the octave definitions. this yields the value for the octave divider m. the value for r is determined by the reference frequency and the received bit rate (see section reference clock programming). table 4 octave de?nition table 5 most-common optical transmission protocols the values for n and k are derived from the division ratio (n.k). the division ratio (n.k) can be calculated with the following formula: where: n = integer part of the division ratio k = fractional part of the division ratio bit rate = bit rate at serial input in mbit/s m = octave divider m r = reference divider r f ref = reference frequency in mhz. octave m lowest bit rate (mbit/s) highest bit rate (mbit/s) 0 1 1800 3200 1 2 900 1800 2 4 450 900 3 8 225 450 4 16 112.5 225 5 32 56.25 112.5 6 64 28.125 56.25 handbook, halfpage 28.125 56.25 112.5 225 450 654 3 2 1 0 900 1800 mbits/s 3200 mgu316 fig.7 commonly used line rates and allocation of octaves along a logarithmic bit rate scale. protocol bit rate (mbit/s) octave 10ge 3125.00 0 2xhdtv 2970.00 0 stm16/oc48 + fec 2666.06 0 stm16/oc48 2488.32 0 dv-6000 2380.00 0 fibre channel 2125.00 0 hdtv 1485.00 1 d-1 video 1380.00 1 dv-6010 1300.00 1 gigabit ethernet 1250.00 1 fibre channel 1062.50 1 opticonnect 1062.50 1 isc 1062.50 1 stm4/oc12 622.08 2 dv-6400 595.00 2 fibre channel 425.00 3 opticonnect 265.63 3 fibre channel 212.50 4 escon/sbcon 200.00 4 stm1/oc3 155.52 4 fddi 125.00 4 fast ethernet 125.00 4 fibre channel 106.25 5 oc1 51.84 6 n.k bit rate m r f ref --------------------------------------- - =
2003 dec 16 13 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw handbook, full pagewidth bit rate m r f ref n.k = n is integer part k is fractional part k = 0 ? no no no no no no yes yes yes yes yes calculate n and k rxnilfrac = 0 rxnilfrac = 1 n = 2 n k j = 1 k j = 0 n = 2 n n = 2 n + 1 n = 2 n - 1 k = k + 0.5 j = 21 k = k 2 k 3 1 ? k 0.25 ? 0.25 < k < 0.75 end decimal to binary conversion of fractional part mce413 k = k - 1 j = j - 1 write k j into registers c3h, c4h, c5h or e3h, e4h, e5h convert n to binary and write into registers c1h, c2h or e1h, e2h j = 0 ? yes k 0 = 1 k = k - 0.5 k 3 0.75 ? fig.8 flowchart for calculating n and k.
2003 dec 16 14 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw having calculated the division factor (n.k), the values for n and k can be calculated according to the flow depicted in the flowchart of fig.8. the value of the octave divider m is programmed by bits rxdiv_m[2:0] in register rxoctdiv (c0h). the value for the main divider n is programmed by bits rxn[8:0] in registers rxmaindiv1 (c1h) and rxmaindiv0 (c2h). the value for the fractional divider k is programmed by bits rxk[21:0] in registers rxfracn2 to rxfracn0 (c3h to c5h). bit rxnilfrac in register rxfracn2 (c3h) must be set depending on whether there is a fractional part or not. example 1 : an sdh or sonet link has a bit rate of 2488.32 mbit/s (stm16/oc48) and consequently fits in octave number 0, so m = 1. suppose the reference frequency provided at pins cref(q) is 77.76 mhz. this means that the reference division r needs to be 4. the values of n and k can be calculated from the flowchart: since k = 0 in this example, no fractional functionality is required, bit rxnilfrac (register c3h), should be logic 1. n=2 n and no correction is required. consequently the appropriate values are: r = 4 (register a1h), m = 1 (register c0h) and n = 256 (registers c1h and c2h). example 2 : an sdh stm16 or sonet oc48 link with fec has a bit rate of 2666.057143 mbit/s (15/14 2488.32 mbit/s) and consequently fits in octave number 0, so m = 1. suppose the reference frequency provided at pins cref(q) is 38.88 mhz. this means that the reference division r needs to be 2. the values of n and k can be calculated from the flowchart: this means that n = 137, k = 0.1428571 and bit rxnilfrac (register c3h) should be logic 0. since k < 0.25, k is corrected to 0.6428571, while the corrected n becomes n = 273. consequently the appropriate values are: r = 2 (register a1h), m = 1 (register c0h), n = 273 (registers c1h and c2h) and k = 10 1001 0010 0100 1001 0011 (registers c3h to c5h). the fec bit rate is usually quoted to be 2666.06 mbit/s. due to round off errors, this leads to a slightly different value for k than in the example. example 3 : a fibre channel link has a bit rate of 1062.50 mbit/s and consequently fits in octave number 1, so m = 2. suppose the reference frequency provided at pins cref(q) is 19.44 mhz. this means that the reference division r needs to be 1. the values of n and k can be calculated from the flowchart: this means that n = 109, k = 0.3107 and bit rxnilfrac should be logic 0 (register c3h). since k is between 0.25 and 0.75, k does not need to be corrected and n = 2 n = 218. consequently the appropriate values are: r = 1 (register a1h), m = 2 (register c0h) and n = 218 (registers c1h and c2h). k = 01 0011 1110 0010 1000 0001 (registers c3h to c5h). example 4 : a non standard transmission link has a bit rate of 3012 mbit/s and consequently fits in octave number 0, so m = 1. suppose the reference frequency provided at pins cref(q) is 20.50 mhz. this means that the reference division r needs to be 1. the values of n and k can be calculated from the flowchart: this means that n = 146, k = 0.9268293 and bit rxnilfrac should be logic 0 (register c3h). since k is larger than 0.75, k needs to be corrected to 0.4268293 and n = 2 n + 1 = 293. consequently the appropriate values are: r = 1 (register a1h), m = 1 (register c0h) and n = 293 (registers c1h and c2h). k = 01 1011 0101 0001 0010 1011 (registers c3h to c5h). if the i 2 c-bus is not used, the dcr can be set up for the eight pre-programmed bit rates by pins dr0 to dr2 with an applied reference frequency of 19.44 mhz (see table 3). n.k bit rate m r f ref --------------------------------------- - 2488.32 mbits 1 4 77.76 mhz -------------------------------------------------------- - 128 == = n.k bit rate m r f ref --------------------------------------- - 2666.05714283 mbits 1 2 38.88 mhz ---------------------------------------------------------------------------- - 137.1428571 == = n.k bit rate m r f ref --------------------------------------- - 1062.50 mbits 2 1 19.44 mhz -------------------------------------------------------- - 109.3106996 == = n.k bit rate m r f ref --------------------------------------- - 3012 mbits 1 1 20.50 mhz ------------------------------------------------ 146.9268293 == =
2003 dec 16 15 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw reference clock programming the reference clock, connected to pins cref(q), is used for both the dcr frequency window detector and the transmitter synthesizer. the reference clock is divided by divider r. pre-programmed operating in an sdh/sonet application assumes the use of a reference clock with a frequency that is a multiple (r) of 19.44 mhz. for other applications, any reference frequency between 18 and 21 mhz may be used. if a reference frequency is selected, any bit rate between 30 mbit/s and 3.2 gbit/s is supported. the division ratio and reference frequency can be programmed by the bits frefi2c[2:0] of register refdiv (a1h) or by pins fref0 and fref1. internally, the reference frequency is always divided to the lowest frequency range between 18 and 21 mhz and for sdh/sonet applications to 19.44 mhz. this is done by divider r which is set by the described pins and bits. in the pre-programmed mode (table 6) four ranges of clock frequencies can be used by programming r through pins fref0 and fref1. in i 2 c-bus mode (table 7) two additional ranges of clock frequencies can be used by programming r through bits frefi2c[2:0]. table 6 truth table for reference divider r in pre-programmed mode table 7 truth table for reference divider r in i 2 c-bus mode reference input for optimum jitter performance and power supply rejection ratio (psrr), the sensitive reference input should be driven differentially (see fig.9). if the reference frequency source (f ref ) is single-ended, the unused cref or crefq input should be terminated with an impedance which matches the source impedance r source . the psrr can be improved by ac coupling the reference frequency source to inputs cref and crefq. any low frequency noise injected from the f ref power supply will be attenuated by the resulting high-pass filter. the low cut-off frequency of the ac coupling must be lower than the reference frequency, otherwise the reference signal will be attenuated and the signal to noise ratio will be reduced. the value of coupling capacitor c is calculated using the formula: prescaler outputs the prescaler output rxprscl(q) is the vco frequency of the dcr divided by the main division factor n. it can be used as an accurate reference for another pll, since it corresponds to the recovered data rate. if needed, the polarity of the prescaler outputs can be inverted by bit rxprsclinv of register ddr&rxprscl (d5h). if no prescaler information is desired, the output can be disabled by bit rxprsclen of the same register. apart pin division factor r reference frequency fref1 fref0 sdh/sonet (mhz) range (mhz) high high 1 19.44 18 to 21 high low 2 38.88 36 to 42 low high 8 155.52 144 to 168 low low 32 622.08 576 to 672 bit division factor r reference frequency range (mhz) fref i2c2 fref i2c1 fref i2c0 0001 18 to 21 0012 36 to 42 0104 72 to 84 0118 144 to 168 10016 288 to 336 10132 576 to 672 c 1 2 p r source f ref ----------------------------------- > handbook, halfpage mdb060 50 w 50 w v cc v ccd cref r source f ref r source c off-chip on-chip c crefq 43 42 fig.9 reference input with single-ended clock source.
2003 dec 16 16 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw from these settings, the signal amplitude can be set. this parameter follows the settings of the lvds outputs. for programming details, see section lvds outputs. fwd programming the default width of the window for frequency acquisition is 1000 ppm around the required bit rate. this window size can be changed between 4000 and 250 ppm by bits winsize[2:0] of register dcrcon (c6h). this allows for loose or tight coupling of the vco to the applied reference clock. another feature is to define a window width of 0 ppm, by means of pin winsize, see table 8. this effectively removes the dead zone from the fwd, rendering the fwd into a classical pll. the vco will be directly locked to the reference signal instead of the incoming bit stream. apart from pin winsize, this mode can be invoked by bits i2cwinsize and winsize of register dcrcon(c6h). table 8 truth table for pin winsize accurate clock generation during loss of signal a zero window size is especially interesting in the absence of input data, since the frequency of the recovered clock will be equal to the programmed line clock rate. bit autowin of register dcrcon (c6h) (see table 9) makes the window size dependent on the los status of the limiter. if the optical input signal is lost, the fwd automatically selects the 0 ppm window size; i.e. a direct lock to the reference frequency. this results in a stable and defined output clock during los situations, while automatically reverting back to normal dcr operating when the input signal returns. the accuracy of the reference frequency needs to be better than 20 ppm if the application has to comply with itu-t recommendations. table 9 truth table for bit autowin inwindow output the status of the fwd circuit is reflected in the state of pin inwindow; high for an in window situation and low whenever the vco is outside the defined frequency window. due to the fact that the device enters the frequency acquisition mode when out of window is detected, the inwindow pin will have an intermittent value when the input signal is not within the defined window boundary. d emultiplexer the demultiplexer converts the serial input bit stream to a parallel format. the output data is available on a 4-bit lvds-bus, thus reducing the data frequency by a factor four. apart from the de-serializing function, the demultiplexer comprises a parity calculator and a frame header detection circuit. the calculated parity (even) is available at output pins rxpar(q), whereas occurrence of the frame header pattern in the data stream results in a one clock cycle (parallel clock output) wide pulse on output pins rxfp(q). if pin enba is high, automatic byte (word) alignment takes place, formatting the parallel output to logical nibbles. apart from pin enba, this mode can be invoked by bits i2cenba and enba of register dmxcon (b8h). to support most commonly used transmission protocols, the frame header pattern can be programmed to any 32-bit pattern (see section frame detection). if required, the demultiplexer output can be forced into a fixed logic state by bit dmxmute of register dmxcon (b8h). the highest supported parallel bus speed is 800 mbit/s. frame detection byte alignment is enabled if the enable byte alignment input (pin enba) is forced high. whenever a 32-bit sequence matches the programmed header pattern, the incoming data is formatted into logical bytes (being output as nibbles) and a frame pulse is generated on differential output pins rxfp(q). any header pattern can be programmed through registers header3 to header0 (b0h to b3h). it is possible to enter a dont care for any bit position, e.g. to program a header pattern that is much shorter than 32 bits or to program a pattern with a gap in it. winsize frequency window (ppm) low 0 high 1000 autowin frequency window 0 fwd user de?ned 1 fwd dependent on los
2003 dec 16 17 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw handbook, full pagewidth x 0 0 1 0 x 1 1 0 0 0 header3 headerx3 received data data stream headerx0 mgu548 header0 msb header lsb header bit 31 1 0 1 1 1 01100010 00000011 011000xx bit 0 1 0 0 0 0 1 0 0 fig.10 example of programming the frame pattern (the symbol x represents a dont care). for this, it is necessary to program registers headerx3 to headerx0 (b4h to b7h). programming a logic 1 into the headerx register will turn the corresponding bit in the header register into a dont care bit, in this way the header register is masked. an example of programming the framing pattern is shown in fig.10. the default frame header pattern is f6f62828h, corresponding to the middle section of the standard sdh/sonet frame header (the last two a1 bytes plus the first two a2 bytes). if signal enba is low, no active alignment takes place. however, if the framing pattern happens to occur in the formatted data, a frame pulse will continue to be output on pins rxfp(q). receiver framing in sdh/sonet applications figure 11 shows a typical sdh/sonet re-frame sequence involving byte alignment. frame and byte boundary detection is enabled on the rising edge of enba and remains enabled while enba is high. boundaries are recognized on receipt of the second a2 byte and rxfp goes high for one rxpc clock cycle. the four most significant bits of the first a2 byte in the frame header are the first bits that appear on the outgoing data bus (rxpd0 to rxpd3) with the correct alignment. when interfacing with a section terminating device, enba must remain high for a full frame after the initial frame pulse. this is to allow the section terminating device to verify internally that frame and byte alignment are correct (see fig.12). byte boundary detection is disabled on the first rxfp pulse after enba has gone low. figure 13 shows frame and byte boundary detection activated on the rising edge of enba and deactivated by the first rxfp pulse after enba has gone low.
2003 dec 16 18 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw handbook, full pagewidth mgu342 valid data invalid data serial clock enba serial data rxpd0 to rxpd3 rxpc rxfp a1 a1 a1 a2 a2 a2, bits 0-3 fig.11 frame and byte detection in sdh/sonet application. handbook, halfpage mce414 enba rxfp boundary detection enabled fig.12 enba operating time with section terminating device. handbook, halfpage mce415 enba rxfp boundary detection enabled fig.13 alternate enba timing. receiver framing in other applications in other applications frame headers may be used that are shorter than 32 bits, e.g. 10 bits for gigabit ethernet. the position of the frame header in the header register can be chosen freely, but determines the boundary of the parallel data on pins rxpd0(q) to rxpd3(q). after alignment, the header bits that are programmed by bits h12 to h15 of register header1 (b2h), appear at the rxpd(q) outputs. a frame pulse appears at output rxfp(q) at the same time. parity generation outputs rxpar(q) provide the even parity of the nibble that is currently available on the parallel bus. with bit rxparinv of register rxmfoutc0 (d4h), the parity can be made odd. if no parity check is required, bit rxparen of register rxmfoutc0 (d4h) can be programmed to disable this output, to reduce power dissipation.
2003 dec 16 19 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw transmitter c lock synthesizer the transmitter frequency can be set independently of the receiver frequency. for this a clock synthesizer is provided that drives the multiplexer. just like the dcr the clock synthesizer is built around a fractional n synthesizer offering a-rate functionality for the transmit path. the clock synthesizer consists of a vco, several dividers, a phase frequency detector, an integrated loop filter, a lock detection circuit and a prescaler output buffer (see fig.14). the internal vco is phase-locked to the reference clock signal provided at pins cref(q). this frequency is internally scaled down (if necessary) to a frequency in the range of 18 to 21 mhz by divider r. because of the 22 bits fractional n capability, any combination of bit rate (30 mbit/s to 3.2 gbit/s) and reference frequency between 18 and 672 mhz is possible. the lsb (bit k0) of the fractional divider, should be set to logic 1 to avoid limit cycles. these are cycles of less than maximum length, which generate spurs in the frequency spectrum. this leaves bits k[21:1] available for programming the fraction, allowing approximately 10 hz of frequency resolution without altering the reference frequency. to meet most transmission standards, the reference frequency should be very accurate. in order to be able to synthesize a clean rf clock that is compliant with the most stringent jitter generation requirements, it should also be very clean in terms of phase noise. handbook, full pagewidth mgu682 n charge pump and loop filter main divider n, k octave divider divided cref(q) txprscl(q) vco to lm mux and multiplexer phase frequency detector up lol down m fig.14 schematic diagram of the clock synthesizer.
2003 dec 16 20 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw all parts of the pll are internal; no external components are required. this allows for easy application. programming the clock synthesizer involves four dividers: reference divider r main divider n fractional divider k octave divider m. this is essentially the same as for the dcr. the first step is to determine in which octave the desired bit rate fits, see tables 4 and 5 and fig.7. figure 7 shows the position of the most commonly used line rates in relation to the defined octaves of the tza3015hw. table 5 clarifies the octave definitions; this yields the value for the octave divider m. the value for r is determined by the reference frequency and the received bit rate (see section reference clock programming). prescaler output the prescaler output txprscl(q) is the vco frequency of the synthesizer divided by the main division factor n. if the synthesizer is in-lock, the frequency is equal to the reference frequency at cref(q) divided by r. it can be used as an accurate reference for another pll. if needed, the polarity of the prescaler outputs can be inverted by bit txprsclinv of register txmfoutc (f2h). if no prescaler information is desired, the output can be disabled by bit txprsclen of the same register. apart from these settings, the signal amplitude can be set. this parameter follows the settings of the lvds outputs. for programming details, see section lvds outputs. loss of lock during operating, the loss of lock output pin lol should be low which means that the clock synthesizer is in-lock and the output frequency corresponds to the programmed value. if pin lol goes high, phase and/or frequency lock is lost and the output frequency may deviate from the programmed value. the lol condition is also available in the registers interrupt (00h) and status (01h). on demand (interrupt is default masked), it generates an interrupt signal at pin int. m ultiplexer the multiplexer comprises a high-speed input register, a 4-stage first in first out (fifo) elastic buffer, a parity check circuit and the actual multiplexing tree. parallel bus clocking schemes the tza3015hw supports both co-directional and contra-directional clocking schemes for the parallel data bus. the clocking application can be selected by pin clkdir or by the bit clkdir of register muxcon0 (f1h). co-directional clocking is default. table 10 truth table for clocking scheme in the co-directional clocking mode, the parallel clock signal is applied to pins txpc(q). the parallel clock signal is generated in the data processing device (e.g. a framer). the co-directional application is depicted in fig.15. the data processing device may be clocked by an external crystal or by the parallel clock output txpco(q) of the tza3015hw. this clock output is internally derived from the synthesizer. if the parallel clock output txpco(q) is not required, it can be disabled in order to save dissipation. this is done by programming bit txpcoen of register txmfoutc (f2h). in a contra-directional clock application, no clock is provided on pin txpc (see fig.16). the clock that samples the input data on the parallel bus, is an internal clock derived from signal txpco. in this application, the part providing the parallel data has to be clocked with the clock signal txpco(q). in order to alleviate timing problems, the phase of clock txpco(q), with respect to the internal clock, can be shifted in 90 steps. bit txpcoinv (180 ) of register txmfoutc (f2h) together with bit txpophase (90 ) of register muxcon0 (f1h) sets the phase shift (see table 11). table 11 truth table for bits txpcinv and txpophase pin clkdir bit clkdir application low 0 contra-directional clocking high 1 co-directional clocking txpcoinv txpophase phase shift 000 0190 1 0 180 1 1 270
2003 dec 16 21 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw handbook, full pagewidth mgu684 txpar txparq framer tza3015hw tx_parity txpd0 to txpd3 txpd0q to txpd3q tx_data txpc txpcq txpco txpcoq tx_clk tx_clk_src system clock fiforeset cref 4 4 fig.15 co-directional clocking diagram. handbook, full pagewidth mgu685 framer tza3015hw tx_parity tx_data tx_clk_src system clock fiforeset cref txpar txparq txpd0 to txpd3 txpd0q to txpd3q txpco txpcoq 4 4 fig.16 contra-directional clocking diagram.
2003 dec 16 22 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw double data rate mode usually the parallel clock frequency (txpc, rxpc and txpco) equals the parallel data rate (for example when the serial bit rate is 2.488 gbit/s, the parallel bit rate is 622 mbit/s and the data is clocked with a 622 mhz clock). this is the default operating mode. however, in some applications it is required to use a parallel clock operating at a frequency that is half of the parallel data rate. this is the ddr mode (for example when the serial bit rate is 2.488 gbit/s, the parallel bit rate is 622 mbit/s and the data is clocked at both the rising as well as the falling edge of the 311 mhz clock). the timing for the parallel input interface is in accordance with the sfi4 specification. the ddr functionality can be enabled by pin enddr (see table 12) or via the i 2 c-bus. i 2 c-bus control is enabled by setting bit i2cddr of register ddr&rxprscl (d5h). in i 2 c-bus mode the three parallel clocks can be set separately in the ddr mode by bits rxpcddren, txpcddren and txpcoddren of registers ddr&rxprscl (d5h), muxcon0 (f1h) and txmfoutc (f2h) respectively (see tables 13, 14 and 15). the ddr mode is functional for the whole bit-rate range, so it is true a-rate. table 12 truth table for pin enddr table 13 truth table for bit rxpcddren table 14 truth table for bit txpcddren table 15 truth table for bit txpcoddren fifo register in the co-directional clocking scheme, the input register samples the parallel bus data on the rising edge of the clock signal txpc(q). the same clock writes this data into the fifo register. data is retrieved from the fifo by an internal clock, derived from the clock generator of the actual multiplexing tree. this provides for large jitter tolerance on the parallel interface; the fifo absorbs momentary phase disturbances. excessively large phase disturbances may stretch the elastic buffer to its limits, causing a fifo overflow or underflow. pin overflow and the registers status (01h) and interrupt (00h) indicate this situation. on demand (i.e to programmed in the register intmask [a0h]) it generates an interrupt signal at pin int. the overflow alarm persists until the fifo is reset by a high-level on pin fiforeset or by setting bit fiforeset of register muxcon0 (f1h) to logic 1. a fiforeset also initializes the fifo. i 2 c-bus control of the fiforeset function is obtained by programming bit i2cfifores of register muxcon0 (f1h). to fully benefit from the fifo, it should be reset whenever there has been a lol condition, or when bit rates have changed. the asynchronous signal fiforeset is re-timed by the internal clock from the clock generator. two clock cycles after signal fiforeset has been made high, the fifo initializes. two clock cycles after signal fiforeset has been made low, the fifo will be operational again. to initialize automatically, when an overflow has occurred, it is possible to connect pin overflow to pin fiforeset directly or via a resistor. multiplexing bus swap bit txbusswap of register muxcon1 (f0h) swaps the bus order of the parallel data input bus txpd0(q) to txpd3(q). bit txbusswap reverses the order of bits from msb to lsb, or vice versa, to allow for optimum connectivity on the pcb. enddr mode low txpc, rxpc and txpco in normal mode high txpc, rxpc and txpco in ddr mode rxpcddren mode 1 rxpc in ddr mode 0 rxpc in normal mode txpcddren mode 1 txpc in ddr mode 0 txpc in normal mode txpcoddren mode 1 txpco in ddr mode 0 txpco in normal mode
2003 dec 16 23 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw parity checking in order to check the integrity of the data provided on the parallel input bus, a parity checking function has been implemented in the tza3015hw. the calculated parity, based on the data currently on the bus, is compared to the expected parity provided at pins txpar(q). if these do not match, i.e. a parity error has occurred, the output pins txparerr(q) are high during the next parallel bus clock (txpc) period. odd or even parity checking can be selected by pin pareven or by bit txpareven of register muxcon1 (f0h). i 2 c-bus control of the parity type is enabled by setting bit i2ctxpareven of register muxcon1 (f0h). a high-level on pin pareven corresponds with even parity (default for bit txpareven), see table 16. table 16 truth table for parity setting jitter performance the clock synthesizer has been optimized for lowest jitter generation and the data and clock recovery has been optimized for the best jitter tolerance. for all sdh/sonet line rates, the jitter tolerance and the jitter generation is compliant with itu-t standard g.958, provided the reference clock is clean enough. for optimum jitter generation, the single-sideband phase noise of the reference frequency should be less than - 140 dbc/hz, for frequencies greater than 12 khz from the carrier. if the reference divider r is used, this requirement elevates with approximately 20 log r. con?guring the main functionality o perating modes the tza3015hw can be configured in several operating modes. it can be configured as: transceiver transmitter receiver transponder with clean-up pll. the transceiver configuration is the default operating mode. the transmitter and receiver part can be enabled independently. this saves power when only one half of the functionality is needed. the tza3015hw can also be configured as a clean-up pll. this is described in the section loop modes. the operating modes can be selected with pins enrx and entx, these pins enable the receiver and the transmitter. this also offers the possibility to power-down the complete ic. operating (or enable) modes are listed in table 17. table 17 truth table for the operating modes l oop modes the tza3015hw supports four loop modes: line loop back diagnostic loop back serial loop timing clean-up loop back. selecting the loop modes the required loop mode can be selected either by pins lm0, lm1 and lm2 or by i 2 c-bus control. the pin settings for the loop mode selection can be seen in table 18. table 18 loop mode selection; note 1 note 1. the loop mode can be also programmed by setting bits lm[2:0] in register loopmode (a3h). pin pareven bit txpareven parity type low 0 odd high 1 even enrx entx operating mode low low power-down low high transmitter high low receiver high high transceiver (or transponder) lm2 lm1 lm0 mode low low low normal low low high line loop back low high low diagnostic loop back high low high serial loop timing high high low clean-up loop back high high high normal
2003 dec 16 24 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw line loop back mode this mode feeds back the received serial data to the serial data output together with the recovered serial clock. this allows testing of the serial data path including the optic fibres. the received serial data that is fed back is also available in parallel format at the parallel output bus (see fig.17). diagnostic loop back mode this mode feeds back the parallel input data to the parallel outputs together with a parallel clock. the parallel data is serialized and available at the serial output. also a serial transmit clock is generated. the parallel output clock signal is recovered from the serial output data. this loop mode is used to test the connection between the transceiver and the data processing unit and the system itself. no external fibre optic connection is needed to test the system (see fig.18). serial loop timing mode this mode feeds back the recovered clock to the clock synthesizer in order to run the receiver and transmitter at the same clock frequency (see fig.19). handbook, full pagewidth mce416 4 4 4 4 4 synthesizer multiplexer parallel data parallel clock parallel data parallel clock serial data serial data serial clock demultiplexer dcr limiter data clock data clock fig.17 line loop back mode. handbook, full pagewidth mce417 4 4 4 4 4 synthesizer multiplexer parallel data parallel clock parallel data parallel clock serial data serial data serial clock demultiplexer dcr limiter data clock data clock fig.18 diagnostic loop back mode.
2003 dec 16 25 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw handbook, full pagewidth mce418 4 4 4 4 4 synthesizer multiplexer parallel data parallel clock parallel data parallel clock serial data serial data serial clock demultiplexer dcr limiter data clock data clock fig.19 serial loop timing mode. clean-up loop back mode the tza3015hw can be used in transponder applications. in this application, the transmitter is locked onto the recovered clock from the dcr (rxprscl). without preparations, the jitter transfer of this application is determined by cascading the transfer functions of the dcr and the clock synthesizer. this transfer function is not well controlled and may not meet the required specification in terms of bandwidth and/or jitter peaking. a second drawback is that the jitter generation of the synthesizer is degraded because the frequency reference (i.e. the dcr) is not very clean in terms of phase-noise. to improve both the jitter transfer and jitter generation in transponder applications, an external low-noise reference oscillator is locked onto the dcr recovered clock by means of a small band pll, i.e. the clean-up pll. the low-noise oscillator, e.g. a voltage controlled crystal oscillator (vcxo), acts as the reference for the clock synthesizer. if appropriately designed, the jitter will be dominated by the clean-up pll. this pll can be optimized for bandwidth and jitter peaking, while the jitter generation is optimized by choosing the appropriate vcxo. figure 20 shows a typical clean-up pll application. for ease of use, all components are integrated in the tza3015hw, except for the vcxo and the loop filter components. the pll consists of a phase frequency detector, a charge pump, an external loop filter (r, c1 and c2), a vcxo and a reference divider. the combination of r and c1 is mandatory and will transform the current at the output of the charge pump into a control voltage for the vxco. capacitor c2 is optional. the internal clock and data path in the tza3015hw is clarified in fig.21. as can be seen in the clean-up application, the received (and transmitted) data is also available in parallel format at the parallel output bus. two bits are available to ease the design of the clean-up pll. the loop is designed to work with a vcxo that has a positive gain. that is an increasing voltage on the vcxo control input will increase the output frequency. by means of bit cluppllinv of register refdiv (a1h) the loop is inverted and will work with vcxos which have a negative gain. bit cluppllhg of register refdiv (a1h) will change the gain of the charge pump. if bit cluppllhg is logic 0, the charge pump current i cp is 100 m a. if bit cluppllhg is logic 1, the charge pump current i cp is 1 ma. this eases choosing suitable component values for r and c1.
2003 dec 16 26 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw handbook, full pagewidth mce419 phase frequency detector i 2 c bit: cluppllinv i 2 c bit: cluppllhg charge pump ipump from dcr cref c1 r c2 vcxo e.g. vectron vdsgla type reference divider to synthesizer external components fig.20 clean-up pll application with the tza3015hw. handbook, full pagewidth mce420 4 4 4 4 4 synthesizer multiplexer parallel data parallel clock parallel data parallel clock serial data serial data serial clock demultiplexer dcr limiter data clock data clock fig.21 clean-up loop back mode. i/o con?guration lvds outputs several options exist that allow flexible configuration of the lvds outputs: output amplitude, signal polarity, bus order, mute and selective enable/disable of various outputs. all these options can be set in the registers mfobcon (a4h), dmxcon (b8h), rxmfoutc0 (d4h), ddr&rxprscl (d5h) and txmfoutc (f2h). affected by these registers are: parallel clock output; pins rxpc(q) parallel data output; pins rxpd0(q) to rxpd3(q) frame pulse output; pins rxfp(q) parity output; pins rxpar(q) parity error output; pins txparerr(q) transmitter parallel clock output; pins txpco(q) prescaler dcr output; pins rxprscl(q) prescaler synthesizer output; pins txprscl(q). the output swing of all lvds outputs can be set by pin lowswing or by programming bit lowswing in register mfobcon (a4h). i 2 c-bus control is enabled by programming bit i2clowswing in register mfobcon (a4h). the typical voltage levels are given in table 19. see also figs 34 and 35. table 19 truth table for pin lowswing lowswing lvds output voltage swing low 500 mv high 300 mv
2003 dec 16 27 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw parallel clock output bit rxpcinv of register rxmfoutc0 (d4h) sets the polarity of the parallel clock output rxpc(q), effectively shifting the clock edge by half a clock cycle and changing the rising edge to a falling edge. this might resolve a parallel bus timing problem. the parallel clock output can be disabled by programming bit rxpcen of register rxmfoutc0 (d4h). parallel data output the parallel output bus data rxpd0(q) to rxpd3(q) can be swapped by bit rxbusswap of register dmxcon (b8h). the mute option forces the parallel output bits to a logic 0 state. this is done by programming bit dmxmute of register dmxcon (b8h). the polarity of the data rxpd0(q) to rxpd3(q) can be set by bit rxpdinv of register rxmfoutc0 (d4h). the data outputs can be disabled by programming bit rxpden of register rxmfoutc0 (d4h). frame pulse output the polarity of the frame pulse output rxfp(q) is set by bit rxfpinv of register rxmfoutc0 (d4h). the frame pulse output can be disabled by programming bit rxfpen of register rxmfoutc0 (d4h). parity output the polarity of the parity output rxpar(q) is set by bit rxparinv of register rxmfoutc0 (d4h). the parity output can be disabled by programming bit rxparen of register rxmfoutc0 (d4h). parity error output the polarity of the parity error output txparerr(q) is set by bit txparerrinv of register txmfoutc (f2h). the parity error output can be disabled by programming bit txparerren of register txmfoutc (f2h). transmitter parallel clock output bit txpcoinv of register txmfoutc (f2h) sets the polarity of the parallel clock output txpco(q), effectively shifting the clock edge by half a clock cycle and changing the rising edge to a falling edge. the phase of the clock can be shifted by 90 by programming bit txpcophase of register muxcon0 (f1h). the combination of these two bits offers a phase shift range of 0 to 360 , adjustable in four steps (step size 90 ). this might resolve a parallel bus timing problem. the parallel clock output can be disabled by programming bit txpcoen of register txmfoutc (f2h). prescaler dcr output the polarity of the receiver prescaler output rxprscl(q) is set by bit rxprsclinv of register ddr&rxprscl (d5h). the receiver prescaler output can be disabled by programming bit rxprsclen of register ddr&rxprscl (d5h). prescaler synthesizer output the polarity of the transmitter prescaler output txprscl(q) is set by bit txprsclinv of register txmfoutc (f2h). the transmitter prescaler output can be disabled by programming bit txprsclen of register txmfoutc (f2h). lvds inputs the available lvds inputs are: parallel clock input; pins txpc(q) parallel data input; pins txpd0(q) to txpd3(q) parity input; pins txpar(q). the differential lvds inputs can handle any input swing with a minimum of 100 mv (p-p) single-ended. the inputs accept any value between v ee and v cc , i.e. the input buffers are true rail-to-rail. the limiting value of the lvds input current is 25 ma. a differential hysteresis of 25 mv is implemented; see fig.33. parallel clock input bit txpcinv of register muxcon1 (f0h) sets the polarity of the parallel clock input txpc(q), effectively shifting the clock edge by half a clock cycle and changing the rising edge to a falling edge. this could be used to resolve a parallel bus timing problem. parallel data input the order of the parallel output bus data txpd0(q) to txpd3(q) can be programmed by bit txbusswap of register muxcon1 (f0h). bit txpdinv of register muxcon1 (f0h) sets the polarity of the parallel data inputs txpd0(q) to txpd3(q). rf outputs the serial rf outputs are cml type outputs (see figs 31 and 32). several options exist that allow flexible configuration of the rf outputs: output amplitude adjustment, signal polarity, data-clock swap, output termination and selective enable/disable of the clock output. thus, the tza3015hw can be configured so that
2003 dec 16 28 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw connectivity problems with other ics are avoided. unused outputs can be disabled. these options can be programmed in registers txrfoutc1 (f3h) and txrfoutc0 (f4h). the following rf outputs are available: serial data output; pins txsd(q) serial clock output; pins txsc(q). the rf cml data and clock outputs have an adjustable signal amplitude between 70 and 1100 mv (p-p) single-ended in 16 steps. the amplitude can be programmed by setting bits rfs[3:0] of register txrfoutc0 (f4h). the default amplitude is 300 mv (p-p) single-ended. the clock and data outputs can be swapped by programming bit txsdscswap of register txrfoutc1 (f3h). allowing full flexibility in the pcb design. the data and clock outputs can be dc- or ac-coupled to the laser driver. the tza3015hw serial rf outputs can be adapted to this for optimal connectivity by appropriately setting bit rfouttermac of register txrfoutc0 (f4h). dc termination is default. serial clock output the polarity of the serial clock output txsc(q) can be programmed by bit txscinv of register txrfoutc1 (f3h). the serial clock output can be disabled by setting pin entxsc or by programming bit txscen of register txrfoutc1 (f3h) (see table 20). this saves power dissipation in applications where the serial clock is not needed table 20 truth table for serial clock enable in order to control the enabling of the serial clock output by the i 2 c-bus, bit i2ctxscen of register txrfoutc1 (f3h) must be programmed. serial data output the polarity of the serial data output txsd(q) can be programmed by bit txsdinv of register txrfoutc1 (f3h). the data output can be disabled by programming bit txsden of register txrfoutc1 (f3h). r eference clock input the reference clock cref(q) input is shown in fig.36 rf input the serial data inputs are pins rxsd(q). these pins are differential cml type serial rf data inputs. there are no special settings for these inputs. cmos outputs the cmos outputs are all used as logic outputs to indicate the status of the tza3015hw. loss of signal output; pin los frequency window detector output; pin inwindow interrupt output; pin int loss of lock output; pin lol fifo overflow alarm output; pin overflow. a low state equals the ground potential and a high state equals the supply voltage. the int output can be configured as cmos output or as open-drain output (see sections open-drain output and interrupt generation). the output is configured as open-drain output by default. cmos inputs the cmos inputs are all used as logic inputs to configure the tza3015hw: user interface selection input; pin ui data rate selection inputs; pins dr0 to dr2 loop mode selection inputs; pins lm0 to lm2 enable receiver input; pin enrx enable transmitter input; pin entx wide and narrow frequency detect window selection input; pin winsize enable low lvds swing output input; pin lowswing reference frequency selection inputs; pins fref0 and fref1 enable byte alignment input; pin enba fifo reset input; pin fiforeset odd or even parity check input; pin pareven co-directional or contra-directional clocking selection input; pin clkdir enable serial clock input; pin entxsc. pin entxsc bit entxsc serial clock low 0 disabled high 1 enabled
2003 dec 16 29 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw the cmos inputs have an internal pull-up resistance; if the input is left open, a logic high state will be forced internally. in the pre-programmed mode (ui = low), pins dr0 to 2 act as regular cmos inputs. in the i 2 c-bus mode (ui = high), pins scl and sda comply with the i 2 c-bus interface standard. o pen - drain output the tza3015hw contains one open-drain interrupt output pin int. the output type of the interrupt controller can be configured by programming bit intout of register intconf (a5h). the output can be configured as a push-pull cmos output or as an open-drain output. for the open-drain configuration an external pull-up resistor of 3.3 k w is recommended. the polarity can be set by programming bit intpol of register intconf (a5h). i nterrupt generation the tza3015hw features a fully configurable interrupt generator. an interrupt signal can be generated in the following events: loss of signal (los) inwindow temperature alarm loss of lock (lol) fifo overflow or underflow. the aforementioned events generate flags which can be read in register status (01h). each of these flags will generate an interrupt in the interrupt register (00h). if programmed so in the register intmask (a0h) the interrupt register bit(s) will generate an interrupt on pin int. in this mask register each interrupt bit can be masked by writing a logic 0 in the corresponding bit position. the status register shows the present status of the receiver. the interrupt register shows the history of the interrupts and is not affected by the intmask register. bit intout of register intconf (a5h) determines the output type of pin int: standard cmos output or open-drain output. the latter is the default which provides for multiple receivers sharing a common interrupt signal wire with a 3.3 k w pull-up resistor (int is active low in this case). the polarity can be set by programming bit intpol of register intconf (a5h). the interrupt and status register can be polled by an i 2 c-bus read action. after the read action on the interrupt register the interrupt register is reset by clearing the interrupt bits where the alarm is no longer present. if the alarm is still set, the interrupt bit is not cleared after the read action. if an interrupt bit remains set (and if it is not masked) the int pin will keep its interrupt condition active; it will not generate a pulse nor a spike. the i 2 c-bus status register is not reset since it always shows the present status of the receiver. it is important to note that the three reserved bits of the status and interrupt registers can take any value and that they can change during operating. these bits can not be used to obtain information on the status of the ic. power supply connections four separate supply domains (v dd , v ccd , v cco and v cca ) provide isolation between the various functional blocks. each supply domain should be connected to a common v cc via separate filters. all supply domains should be powered synchronously. all supply pins, including the exposed die pad, must be connected. the die pad should be connected with the lowest inductance possible. since the die pad is also used as the main ground return of the chip, the connection should have a low dc impedance as well. the voltage supply levels should be in accordance with the values specified in chapter characteristics. all external components should be surface mounted devices, preferably of size 0603 or smaller. the components must be mounted as closely to the ic as possible. i 2 c-bus i 2 c-bus characteristics the i 2 c-bus is a 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). data transfer may be initiated only when the line is not busy. s tart and stop conditions figure 22 shows the definition of the start and stop conditions. both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p).
2003 dec 16 30 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw a cknowledge figure 23 shows the definition of an acknowledgement on the i 2 c-bus. only one data byte is transferred between the start and stop conditions during a write from the transmitter to the receiver. each byte of eight bits is followed by an acknowledge bit. the acknowledge bit is a high level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges must pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. handbook, full pagewidth mbc622 sda scl p stop condition sda scl s start condition fig.22 start and stop conditions. handbook, full pagewidth mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master fig.23 (not) acknowledge condition on the i 2 c-bus.
2003 dec 16 31 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw i 2 c-bus protocol figure 24 shows the definition of the bytes. if bit r/ w=1 the master reads from the read register, if bit r/ w = 0 the master writes to the write register. it is not possible to write and read the same register. w rite protocol figure 25 shows the protocol for writing to one single register. after the start command (s) the transmitter sends the address of the slave device, waits for an acknowledge from the slave, sends the register address, waits for an acknowledge, sends data, waits for an acknowledge from the master followed by a stop condition (p). r ead protocol figure 26 shows the protocol for reading from one or more registers. after the start command (s) the receiver sends the address of the slave device, waits for an acknowledge from the transmitter slave, receives data from the slave (slave, tza3015hw, starts sending data after generating the acknowledge), after receiving the data, the receiver (master) sends an acknowledge, or if finished a not-acknowledge followed by a stop condition (p). handbook, full pagewidth mce425 msb lsb 1 msb lsb r/w slave address register address fig.24 definition of slave- and register address (= instruction byte); slave and register addresses are 7 bits. handbook, full pagewidth s a1 aa data p acknowledge from slave r/w mdb071 0 register address slave address acknowledge from slave acknowledge from master msb msb lsb one byte transferred fig.25 write protocol. handbook, halfpage s a a/a data p r/w mdb072 1 slave address acknowledge from slave acknowledge from master (1) msb lsb n bytes fig.26 read protocol. (1) the master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave.
2003 dec 16 32 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw i 2 c-bus registers the tza3015hw can be programmed via the i 2 c-bus if pin ui = high or leaving the pin open-circuit. the i 2 c-bus registers can be accessed via the 2-wire i 2 c-bus interface using pins scl and sda if pin cs = high during read or write actions. the i 2 c-bus address of the tza3015hw can be found in table 2. table 21 i 2 c-bus registers address (hex) name function default range r/w general part 00 interrupt interrupt register (see table 22) xxxx xxxx n.a. r 01 status status register (see table 23) xxxx xxxx n.a. r a0 intmask interrupt mask register (see table 24) 0000 0100 n.a. w a1 refdiv reference divider and clean-up pll (see table 25) 0000 0000 n.a. w a3 loopmode loop mode and enable register (see table 26) 0110 0111 n.a. w a4 mfobcon lvds output buffer con?guration (see table 27) 0101 0000 n.a. w a5 intconf interrupt output con?guration (see table 28) 0000 0001 n.a. w transceiver b0 header3 programmable header; msb (see table 29) 1111 0110 n.a. w b1 header2 programmable header (see table 30) 1111 0110 n.a. w b2 header1 programmable header (see table 31) 0010 1000 n.a. w b3 header0 programmable header; lsb (see table 32) 0010 1000 n.a. w b4 headerx3 programmable header dont care; msb (see table 33) 0000 0000 n.a. w b5 headerx2 programmable header dont care (see table 34) 0000 0000 n.a. w b6 headerx1 programmable header dont care (see table 35) 0000 0000 n.a. w b7 headerx0 programmable header dont care; lsb (see table 36) 0000 0000 n.a. w b8 dmxcon demultiplexer con?guration register (see table 37) 0000 0000 n.a. w c0 rxoctdiv dcr octave m divider (see table 38) 0000 0000 n.a. w c1 rxmaindiv1 vco frequency n divider (see table 39) 0000 0001 128 to 511 w c2 rxmaindiv0 vco frequency n divider (see table 40) 0000 0000 128 to 511 w c3 rxfracn2 fractional division (see table 41) 1000 0000 n.a. w c4 rxfracn1 fractional division (see table 42) 0000 0000 n.a. w c5 rxfracn0 fractional division (see table 43) 0000 0000 n.a. w c6 dcrcon dcr con?guration register (see table 44) 0000 1100 n.a. w d0 limlosth limiter loss threshold 0000 0000 0 to 255 w d1 limloscon limiter loss of signal con?guration register (see table 45) 0000 1101 n.a. w d2 limsl limiter slice level 0000 0000 0 to 255 w d3 limcon limiter ampli?er con?guration (see table 46) 0000 0000 n.a. w d4 rxmfoutc0 disable/invert parallel outputs (see table 47) 1010 1010 n.a. w
2003 dec 16 33 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw table 22 register interrupt (address: 00h) d5 ddr&rxprscl disable/invert parallel outputs (see table 48) 0010 0000 n.a. w transmitter part e0 txoctdiv synthesizer octave divider (see table 49) 0000 0000 n.a. w e1 txmaindiv1 vco frequency (n divider) (see table 50) 0000 0001 128 to 255 w e2 txmaindiv 0 vco frequency (n divider) (see table 51) 0000 0000 128 to 255 w e3 txfracn2 fractional division (see table 52) 1000 0000 n.a. w e4 txfracn1 fractional division (see table 53) 0000 0000 n.a. w e5 txfracn0 fractional division (see table 54) 0000 0000 n.a. w f0 muxcon1 multiplexer con?guration byte 1 (see table 55) 0110 0010 n.a. w f1 muxcon0 multiplexer con?guration byte 0 (see table 56) 0000 0010 n.a. w f2 txmfoutc disable/invert lvds outputs (see table 57) 1010 1000 n.a. w f3 txrfoutc1 disable/invert rf outputs (see table 58) 0100 1011 n.a. w f4 txrfoutc0 rf output con?guration register (see table 59) 0000 0011 n.a. w bit parameter 76543210 description name loss of signal los 1 no signal present 0 signal present inwindow inwindow 1 frequency out of window 0 frequency in window temperature alarm talarm 1 junction temperature 3 130 c 0 junction temperature <130 c loss of lock lol 1 synthesizer out of lock 0 synthesizer out of lock xxx reserved fifo over?ow or under?ow overflow 1 fifo overflow or underflow occurred 0 fifo normal operating address (hex) name function default range r/w
2003 dec 16 34 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw table 23 register status (address: 01h) table 24 register intmask (address: a0h, default value: 04h) bit parameter 76543210 description name loss of signal los 1 no signal present 0 signal present inwindow inwindow 1 frequency out of window 0 frequency in window temperature alarm talarm 1 junction temperature 3 130 c 0 junction temperature <130 c loss of lock lol 1 synthesizer out of lock 0 synthesizer out of lock xxx reserved fifo over- or under?ow overflow 1 fifo under- or underflow occurred 0 fifo normal operating bit parameter 76543210 description name mask los signal mlos 1 not masked 0 masked; note 1 mask inwindow signal minwindow 1 not masked 0 masked; note 1 mask temperature alarm mtalarm 1 not masked 0 masked; note 1 mask lol signal mlol 1 not masked 0 masked; note 1 xxx reserved mask fifo over?ow or under?ow moverflow 1 not masked 0 masked; note 1 00000100 def ault value
2003 dec 16 35 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw note to table 24 1. signal is not processed by the interrupt controller. table 25 register refdiv (address: a1h, default value: 00h) table 26 register loopmode (address: a3h, default value: 67h) bit parameter 76543210 description name reference frequency division ratio divider r; octave selection frefi2c[2:0] 000 r=1 001 r=2 010 r=4 011 r=8 100 r=16 101 r=32 reference frequency division programming by i 2 c-bus i2cfref 1 enable i 2 c-bus programming 0 enable programming by pins x reserved high gain clean-up pll cluppllhg 1 enable high gain 0 normal gain invert charge pump currents of the clean-up pll cluppllinv 1 clean-up pll inverted 0 clean-up pll normal operating enable clean-up pll cluppllen 1 clean-up pll enabled 0 clean-up pll disabled (except in clean-up loop back mode) 00000000 def ault value bit parameter 76543210 description name loop mode selection lm[2:0] 0 0 0 normal mode 0 0 1 line loop back mode 0 1 0 diagnostic loop back mode 0 1 1 reserved 1 0 0 reserved 1 0 1 serial loop timing mode 1 1 0 clean-up loop back mode 1 1 1 normal mode
2003 dec 16 36 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw table 27 register mfobcon (address: a4h, default value: 50h) table 28 register intconf (address: a5h, default value: 01h) loop mode programming by i 2 c-bus i2clm 1 enable i 2 c-bus programming 0 enable programming by pins x reserved enable receiver enrx 1 receiver enabled 0 receiver disabled enable transmitter entx 1 transmitter enabled 0 transmitter disabled transmitter/receiver enable by i 2 c-bus i2centrx 1 enable i 2 c-bus programming 0 enable programming by pins 01100111 def ault value bit parameter 76543210 description name xxxxxx reserved parallel output voltage swing lowswing 1 low swing (300 mv) 0 high swing (500 mv) parallel output voltage swing programming by i 2 c-bus i2clowswing 1 enable i 2 c-bus programming 0 enable programming by pins 01010000 def ault value bit parameter 76543210 description name interrupt output polarity intpol 1 inverted 0 normal operating interrupt output con?guration intout 1 push-pull output 0 open drain output xxxxxx reserved 00000001 def ault value bit parameter 76543210 description name
2003 dec 16 37 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw table 29 register header3 (address: b0h, default value: f6h) table 30 register header2 (address: b1h, default value: f6h) table 31 register header1 (address: b2h, default value: 28h) table 32 register header0 (address: b3h, default value: 28h) table 33 register headerx3 (address: b4h, default value: 00h) table 34 register headerx2 (address: b5h, default value: 00h) bit parameter 76543210 description name xxxxxxxx programmable header; h31 = msb h[31:24] 11110110 def ault value bit parameter 76543210 description name xxxxxxxx programmable header h[23:16] 11110110 def ault value bit parameter 76543210 description name xxxxxxxx programmable header h[15:08] 00101000 def ault value bit parameter 76543210 description name xxxxxxxx programmable header; h00 = lsb h[07:00] 00101000 def ault value bit parameter 76543210 description name xxxxxxxx dont care; hx31 = msb hx[31:24] 00000000 def ault value bit parameter 76543210 description name xxxxxxxx dont care hx[23:16] 00000000 def ault value
2003 dec 16 38 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw table 35 register headerx1 (address: b6h, default value: 00h) table 36 register headerx0 (address: b7h, default value: 00h) table 37 register dmxcon (address: b8h, default value: 00h) bit parameter 76543210 description name xxxxxxxx dont care hx[15:08] 00000000 def ault value bit parameter 76543210 description name xxxxxxxx dont care; hx00 = lsb hx[07:00] 00000000 def ault value bit parameter 76543210 description name xxxx reserved parallel bus swapping rxbusswap 1 rxpd0 = msb; rxpd3 = lsb (swapped) 0 rxpd3 = msb; rxpd0 = lsb (normal) mute parallel outputs dmxmute 1 enable mute; parallel outputs forced to logic 0 0 disable mute enable byte alignment enba 1 byte alignment enabled 0 byte alignment disabled enba programming by i 2 c-bus i2cenba 1 enable i 2 c-bus programming 0 enable programming by pins 00000000 def ault value
2003 dec 16 39 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw table 38 register rxoctdiv (address: c0h, default value: 00h) table 39 register rxmaindiv1 (address: c1h, default value: 01h) table 40 register rxmaindiv0 (address: c2h, default value: 00h) table 41 register rxfracn2 (address: c3h, default value: 80h) bit parameter 76543210 description name division ratio octave divider m; octave selection rxdiv_m[2:0] 0 0 0 m = 1; octave number 0 0 0 1 m = 2; octave number 1 0 1 0 m = 4; octave number 2 0 1 1 m = 8; octave number 3 1 0 0 m = 16; octave number 4 1 0 1 m = 32; octave number 5 1 1 0 m = 64; octave number 6 xxxxx reserved 00000000 def ault value bit parameter 76543210 description name x division ratio divider n; rxn8 = msb rxn8 xxxxxxx reserved 00000001 def ault value bit parameter 76543210 description name xxxxxxxx division ratio divider n; rxn0 = lsb rxn[7:0] 00000000 def ault value bit parameter 76543210 description name xxxxxxfr actional divider; rxk21 = msb rxk[21:16] x reserved rxnilfrac control bit (nf) rxnilfrac 1 no fractional n functionality 0 fractional n functionality 10000000 def ault value
2003 dec 16 40 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw table 42 register rxfracn1 (address: c4h, default value: 00h) table 43 register rxfracn0 (address: c5h, default value: 00h) table 44 register dcrcon (address: c6h, default value: 0ch) table 45 register limloscon (address: d1h, default value: 0dh) bit parameter 76543210 description name xxxxxxxxfr actional divider rxk[15:8] 00000000 def ault value bit parameter 76543210 description name xxxxxxxxfr actional divider; rxk0 = lsb rxk[7:0] 00000000 def ault value bit parameter 76543210 description name frequency window size; relative to bit rate winsize[2:0] 0 1 1 2000 ppm 1 0 0 1000 ppm 1 0 1 500 ppm 1 1 0 250 ppm manual frequency window size selection winsize 1 window size according to bits winsize[2:0] (default value 1000 ppm); pll frequency loosely coupled to reference crystal 0 window size is 0 ppm; pll frequency directly synthesized from reference crystal winsize control bit i2cwinsize 1 through i 2 c-bus interface 0 through external pin winsize automatic frequency window size selection autowin 1 enabled 0 disabled xx reserved 00001100 def ault value bit parameter 76543210 description name enable loss of signal detection losen 1 los detection enabled 0 los detection disabled
2003 dec 16 41 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw table 46 register limcon (address: d3h, default value: 00h) los threshold level programming by i 2 c-bus i2closth 1 enable i 2 c-bus programming; set level by register d0h 0 set level by applying analog reference voltage on pin losth loss of signal detection hysteresis htlcb[2:0] 000 0db 001 1db 010 2db 011 3db 100 4db 101 5db 110 6db 111 7db enable slice level slen 1 slice level enabled 0 slice level disabled slice level sign slsgn 1 positive slice level 0 negative slice level los level polarity lospol 1 inverted polarity 0 normal polarity 00001101 def ault value bit parameter 76543210 description name ampli?er octave selection amp[2:0] 0 0 0 octave number 0; 1800 to 3200 mbit/s 0 0 1 octave number 1; 900 to 1800 mbit/s 0 1 0 octave number 2; 450 to 900 mbit/s 0 1 1 octave number 3; 225 to 450 mbit/s 1 x x octave number 4; 30 to 225 mbit/s xxxxx reserved 00000000 def ault value bit parameter 76543210 description name
2003 dec 16 42 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw table 47 register rxmfoutc0 (address: d4h, default value: aah) table 48 register ddr&rxprscl (address: d5h, default value: 20h) bit parameter 76543210 description name parallel data output polarity rxpdinv 1 inverted 0 normal parallel data output enable rxpden 1 enabled 0 disabled parallel clock output polarity rxpcinv 1 inverted 0 normal parallel clock output enable rxpcen 1 enabled 0 disabled parity output polarity rxparinv 1 inverted 0 normal parity output enable rxparen 1 enabled 0 disabled frame pulse output polarity rxfpinv 1 inverted 0 normal frame pulse output enable rxfpen 1 enabled 0 disabled 10101010 def ault value bit parameter 76543210 description name xxxx reserved invert rx prescaler output rxprsclinv 1 inverted 0 normal enable rx prescaler output rxprsclen 1 enabled 0 disabled
2003 dec 16 43 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw table 49 register txoctdiv (address: e0h, default value: 00h) table 50 register txmaindiv1 (address: e1h, default value: 01h) table 51 register txmaindiv0 (address: e2h, default value: 00h) ddr clock frequency mode for rxpc rxpcddren 1 ddr mode enabled 0 normal operating mode ddr programming by i2c-bus i2cddr 1 enable i2c-bus programming 0 enable programming by pin enddr 00100000 def ault value bit parameter 76543210 description name division ratio octave divider m; octave selection txdiv_m[2:0] 0 0 0 m = 1; octave number 0 0 0 1 m = 2; octave number 1 0 1 0 m = 4; octave number 2 0 1 1 m = 8; octave number 3 1 0 0 m = 16; octave number 4 1 0 1 m = 32; octave number 5 1 1 0 m = 64; octave number 6 xxxxx reserved 00000000 def ault value bit parameter 76543210 description name x division ratio divider n; txn8 = msb txn8 xxxxxxx reserved 00000001 def ault value bit parameter 76543210 description name xxxxxxxx division ratio divider n; txn0 = lsb txn[7:0] 00000000 def ault value bit parameter 76543210 description name
2003 dec 16 44 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw table 52 register txfracn2 (address: e3h, default value: 80h) table 53 register txfracn1 (address: e4h, default value: 00h) table 54 register txfracn0 (address: e5h, default value: 00h) table 55 register muxcon1 (address: f0h, default value: 62h) bit parameter 76543210 description name xxxxxxfr actional divider: txk21 = msb txk[21:16] x reserved txnilfrac control bit (nf) txnilfrac 1 no fractional n functionality 0 fractional n functionality 10000000 def ault value bit parameter 76543210 description name xxxxxxxxfr actional divider txk[15:8] 00000000 def ault value bit parameter 76543210 description name xxxxxxxxfr actional divider; txk0 = lsb txk[7:0] 00000000 def ault value bit parameter 76543210 description name parallel input bus swapping txbusswap 1 txpd0 = msb; txpd3 = lsb (swapped) 0 txpd3 = msb; txpd0 = lsb (normal) parity polarity txpareven 1 even parity 0 odd parity parity programming by i 2 c-bus i2ctxpareven 1 by i 2 c-bus interface 0 by external pin pareven parallel clock input polarity txpcinv 1 inverted 0 normal
2003 dec 16 45 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw table 56 register muxcon0 (address: f1h, default value: 02h) parallel data input polarity txpdinv 1 inverted 0 normal xxx reserved 01100010 def ault value bit parameter 76543210 description name parallel clock output phase txpcophase 190 phase shift 00 phase shift parallel clock direction clkdir 1 co-directional clocking 0 contra-directional clocking parallel clock direction programming i 2 c-bus i2clkdir 1 by i 2 c-bus interface 0 by external pin clkdir fifo reset fiforeset 1 reset fifo 0 normal mode fifo reset programming by i 2 c-bus i2cfifores 1 by i 2 c-bus interface 0 by external pin fiforeset ddr clock frequency mode for txpc txpcddren 1 ddr mode enabled 0 normal mode xx reserved 00000010 def ault value bit parameter 76543210 description name
2003 dec 16 46 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw table 57 register txmfoutc (address: f2h, default value: a8h) table 58 register txrfoutc1 (address: f3h, default value: 4bh) bit parameter 76543210 description name x reserved ddr clock frequency mode for txpco txpcoddren 1 ddr mode enabled 0 normal mode parallel clock output polarity txpcoinv 1 inverted 0 normal parallel clock output enable txpcoen 1 enabled 0 disabled prescaler output polarity txprsclinv 1 inverted 0 normal prescaler output enable txprsclen 1 enabled 0 disabled parity error output polarity txparerrinv 1 inverted 0 normal parity error output enable txparerren 1 enabled 0 disabled 10101000 def ault value bit parameter 76543210 description name x x reserved serial output data polarity txsdinv 1 inverted 0 normal enable serial data output txsden 1 enabled 0 disabled clock and data output swap txsdscswap 1 swapped clock and data output 0 normal clock and data output
2003 dec 16 47 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw table 59 register txrfoutc0 (address: f4h, default value: 03h) serial clock output polarity txscinv 1 inverted 0 normal enable serial clock output txscen 1 enabled 0 disabled serial clock output enable programming by i 2 c-bus i2ctxscen 1 by i 2 c-bus interface 0 by external pin txsc 01001011 def ault value bit parameter 76543210 description name serial output signal amplitude rfs[3:0] 0000 minimum; 70 mv (p-p) 0011 default; 300 mv (p-p) 1111 maximum; 1100 mv (p-p) xx reserved serial output termination rfouttermac 1 ac-coupled 0 dc-coupled x reserved 00000011 def ault value bit parameter 76543210 description name
2003 dec 16 48 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw limiting values in accordance with the absolute maximum rating system (iec 60134). thermal characteristics notes 1. in compliance with jedec standards jesd51-5 and jesd51-7. 2. four-layer printed-circuit board (pcb) in still air with 36 plated vias connected with the heatsink and the second and fourth layer in the pcb. symbol parameter min. max. unit v cc analog supply voltage - 0.5 +3.6 v v dd digital supply voltage - 0.5 +3.6 v v n dc voltage on pins rxpc(q), rxpd0(q) to rxpd3(q), rxfp(q), rxpar(q), txparerr(q), txpco(q), rxprscl(q) and txprscl(q) 0.7 v cc + 0.5 v on pins rxsd(q), cref(q), txpc(q), txpd0(q) to txpd3(q), txpar(q), ui, rref, losth, rssi, los, cs, sda, scl, lm0 to lm2, int, enrx, entx, winsize, inwindow, enddr, lowswing, enba, pareven, overflow, fiforeset, entxsc, txsd(q), txsc(q), lol, fref0, fref1, clkdir and ipump - 0.5 v cc + 0.5 v i n input current on pins rxpc(q), rxpd0(q) to rxpd3(q), rxfp(q), rxpar(q), txparerr(q), txpco(q), rxprscl(q) and txprscl(q) - 20 +20 ma on pins rxsd(q) and cref(q) - 30 +30 ma on pin int - 2+2ma on pins txpc(q), txpd0(q) to txpd3(q) and txpar(q) - 25 +25 ma t amb ambient temperature - 40 + 85 c t j junction temperature - 125 c t stg storage temperature - 65 + 150 c symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient notes 1 and 2 16 k/w
2003 dec 16 49 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw characteristics v cca =v ccd =v cco = 3.14 to 3.46 v; t amb = - 40 to +85 c; r th(j-a) < 16 k/w; all characteristics are speci?ed for the default test settings (see table 60); all voltages are referenced to v ee ; positive currents ?ow into the device; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies i cca analog supply current 13 21 29 ma i ccd digital supply current notes 1 and 2 350 395 456 ma i dd digital supply current 0 0.3 1 ma i cco supply current for clock generator 41 55 64 ma i cc(tot) total supply current notes 1 and 2 404 471 550 ma p tot total power dissipation notes 1 and 2 1.3 1.6 1.8 w cmos inputs: pins ui, cs, dr0 to dr2, lm0 to lm2, enrx, entx, pareven, winsize, lowswing, fref0, fref1, enba, fiforeset, clkdir, entxsc and enddr v il low-level input voltage -- 0.2v cc v v ih high-level input voltage 0.8v cc -- v i il low-level input current v il =0v - 200 --m a i ih high-level input current v ih =v cc -- 10 m a cmos outputs: pins los, int, inwindow, lol and overflow v ol low-level output voltage i ol =1ma 0 - 0.2 v v oh high-level output voltage i oh = - 0.5 ma v cc - 0.2 - v cc v open-drain output: pin int v ol low-level output voltage i ol =1ma 0 - 0.2 v i oh high-level output current v oh =v cc -- 10 m a serial outputs: pins txsd(q) and txsc(q) v o(p-p) default output voltage swing (peak-to-peak value) single-ended with 50 w external load; dc swing; note 3 220 300 380 mv z o output impedance single-ended to v cc 40 50 60 w t r rise time 20% to 80% - 60 90 ps
2003 dec 16 50 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw t f fall time 80% to 20% - 60 90 ps t d-c data-to-clock delay between differential crossovers; see fig.27 - 50 - +50 ps d duty cycle signal txsc(q) between differential crossovers 40 50 60 % f bit output bit rate 30 - 3200 mbit/s serial input: pins rxsd(q) v i(p-p) input voltage swing (peak-to-peak value) single-ended; note 4; prbs (2 7 - 1) 12 - 500 mv v i(sens)(p-p) input voltage sensitivity (peak-to-peak value) single-ended; prbs (2 7 - 1) - 512mv v sl typical slice level range note 5 - 50 - +50 mv z i input impedance differential 80 100 120 w f bit input data rate 30 - 3200 mbit/s lvds outputs: pins rxpd0(q) to rxpd3(q), rxpc(q), rxpar(q), txparerr(q), rxprscl(q),txprscl(q), rxfp(q) and txpco(q) v o(dif) differential output voltage r l = 100 w ; dc-coupled low swing mode, dc 250 300 360 mv high swing mode, dc 400 500 600 mv v o(cm) common mode output voltage r l = 100 w , dc-coupled 1.10 1.22 1.33 v t r , t f rise and fall time c l = 1 pf 100 200 250 ps t d-c data to clock delay normal mode; see fig.28 - 200 - +200 ps ddr mode; see fig.28 1 / 4 t clk - 250 1 / 4 t clk - 50 1 / 4 t clk + 150 ps d rx duty cycle rxpc(q) normal mode 45 50 55 % ddr mode 47 50 53 % d tx duty cycle txpco(q) normal mode 45 50 55 % ddr mode 47 50 53 % skew channel to channel skew rxpd0 to rxpd3, rxpar and rxfp; note 6 -- 100 ps lvds inputs: pins txpd0(q) to txpd3(q), txpar(q) and txpc(q) v i input voltage range 0 - v cc mv v i(th)(dif) differential input voltage threshold dc - 100 - +100 mv symbol parameter conditions min. typ. max. unit
2003 dec 16 51 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw v i(p-p) input voltage swing (peak-to-peak value) single-ended; note 6 -- 1000 mv v i(hys) differential hysteresis input voltage t amb =0 cto85 c25 -- mv t amb = - 40 cto0 c15 -- mv z i(dif) differential input impedance 80 100 120 w t h(co) hold time co-directional clocking see fig.29 - 150 300 ps t su(co) set-up time co-directional clocking see fig.29 - 20 300 ps t h(contra) hold time contra- directional clocking see fig.29 -- 1100 - 850 ps t su(contra) set-up time contra-directional clocking see fig.29 - 1300 1450 ps t h(co)ddr hold time co-directional clocking in ddr mode f bit = 124 to 800 mbit/s; see fig.29 - 0.3t clk + 40 0.3t clk + 240 ps f bit = 30 to 124 mbit/s; see fig.29; note 6 - 4780 5000 ps t su(co)ddr set-up time co-directional clocking in ddr mode f bit = 124 to 800 mbit/s; see fig.29 -- 1 / 4 t clk - 130 - 1 / 4 t clk + 200 ps f bit = 30 to 124 mbit/s; see fig.29; note 6 -- 4560 - 3700 ps t h(contra)ddr hold time contra-directional clocking in ddr mode see fig.29 -- 1 / 4 t clk - 1200 - 1 / 4 t clk - 1000 ps t su(contra)ddr set-up time contra-directional clocking in ddr mode see fig.29 - 1 / 4 t clk + 1400 1 / 4 t clk + 1600 ps d duty cycle clock txpc(q) note 6 40 50 60 % reference frequency input; pins cref(q) v i(p-p) input swing (peak-to-peak value) single-ended 50 - 1000 mv v i input voltage range note 6 v cc - 1 - v cc + 0.25 v z i input impedance single-ended to v cc 40 50 60 w symbol parameter conditions min. typ. max. unit
2003 dec 16 52 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw d f cref reference clock frequency accuracy sdh/sonet requirement - 20 - +20 ppm f cref reference clock frequency see section reference clock programming; r = 1, 2, 4, 8, 16 or 32 18 r 19.44 r21 r mhz reference voltage; pin rref v ref reference voltage 10 k w resistor to v ee 1.17 1.21 1.26 v received signal strength indicator; pin rssi v i(p-p) detectable input voltage swing on serial data input (peak-to-peak value) single-ended 5 - 500 mv s rssi rssi sensitivity see fig.4 15 17 20 mv/db v rssi(32mv) output voltage serial data input voltage v i =32mv; prbs(2 31 - 1) 580 680 780 mv d v o output voltage variation input 30 to 3200 mbit/s; prbs(2 31 - 1); v cc = 3.14 to 3.47 v; d t = 120 c - 50 - +50 mv z o output impedance - 110 w i o(source) output source current -- 1ma i o(sink) output sink current -- 0.4 ma los detector hys hysteresis note 7 - 3 - db t a assert time d v i(p-p) =3db -- 5 m s t d de-assert time d v i(p-p) =3db -- 5 m s clean-up pll: pin ipump i cp(source) charge pump source current cluppllhg = 0 -- 0.1 - ma cluppllhg = 1 -- 1 - ma i cp(sink) charge pump sink current cluppllhg = 0 - 0.1 - ma cluppllhg = 1 - 1 - ma symbol parameter conditions min. typ. max. unit
2003 dec 16 53 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw jitter characteristics j tol(p-p) jitter tolerance to serial data input signal (peak-to-peak value) stm1/oc3 mode; prbs(2 23 - 1) f = 6.5 khz 3 >10 - ui f = 65 khz 0.3 >1 - ui f = 1 mhz 0.3 >0.5 - ui stm4/oc12 mode; prbs(2 23 - 1) f = 25 khz 3 >10 - ui f = 250 khz 0.3 >1 - ui f = 5 mhz 0.3 >0.5 - ui stm16/oc48 mode; prbs(2 23 - 1) f = 100 khz 3 10 - ui f = 1 mhz 0.3 1 - ui f = 20 mhz 0.3 0.5 - ui j gen(p-p) jitter generation at serial data and clock output (peak-to-peak value) stm1/oc3 mode; notes 8 and 9 f = 500 hz to 1.3 mhz -- 16 mui f = 12 khz to 1.3 mhz -- 4 mui f = 65 khz to 1.3 mhz -- 4 mui stm4/oc12 mode; notes 8 and 9 f = 1 khz to 5 mhz -- 63 mui f = 12 khz to 5 mhz -- 13 mui f = 250 khz to 5 mhz -- 13 mui stm16/oc48 mode; note 8 f = 5 khz to 20 mhz - 32 250 mui f = 12 khz to 20 mhz - 30 50 mui f = 1 mhz to 20 mhz - 6 50 mui pll characteristics receiver t acq acquisition time 30 mbit/s; note 6 -- 200 m s t acq(pc) acquisition time at power cycle 30 mbit/s; note 6 -- 10 ms t acq(o) acquisition time octave change 30 mbit/s; note 6 -- 10 m s i 2 c-bus input and output: pins scl and sda v il low-level input voltage -- 0.2v cc v v ih high-level input voltage 0.8v cc -- v symbol parameter conditions min. typ. max. unit
2003 dec 16 54 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw notes 1. for the typical specification lvds outputs: rxpar(q), rxprscl(q), txparerr(q), txpco(q) and txprscl(q) are disabled. also serial output txsc(q) is disabled. 2. the following conditions are valid for the maximum specification and are additional to the default settings: bit cluppllen = 1 (clean-up pll is enabled); bit cluppllhg = 1 (high gain); line loop back is enabled; pin lowswing = low (high swing for lvds outputs); bits rfs[3:0] = 1111 (maximum output swing for txsd(q) and v hys hysteresis of schmitt-trigger inputs note 6 0.05v cc -- v v ol low-level output voltage on pin sda (open-drain) i ol =3ma 0 - 0.4 v i li input leakage current - 10 - +10 m a c i input capacitance note 6 -- 10 pf i 2 c-bus timing ; note 6 f scl scl clock frequency -- 100 khz t low scl low time 1.3 --m s t hd;sta hold time start condition 0.6 --m s t high scl high time 0.6 --m s t su;sta set-up time start condition 0.6 --m s t hd;dat data hold time 0 - 0.9 m s t su;dat data set-up time 100 -- ns t su;sto set-up time stop condition 0.6 --m s t r scl and sda rise time 20 - 300 ns t f scl and sda fall time 20 - 300 ns t buf bus free time between stop and start 1.3 --m s c b capacitive load for each bus line -- 400 pf t sp pulse width of allowable spikes 0 - 50 ns v nl noise margin at low-level 0.1v cc -- v v nh noise margin at high-level 0.2v cc -- v symbol parameter conditions min. typ. max. unit
2003 dec 16 55 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw txsc(q). these maximum settings yield the following maximum specification values: i ccd = 680 ma, i cc(tot) = 774 ma and p tot = 2.7 w. 3. the output swing is adjustable between 70 mv (typical) and 1100 mv (typical) in 16 steps controlled by bits rfs[3:0] of the register txrfoutc0 (f4h). 4. the rf input is protected against a differential overvoltage; the maximum input current is 30 ma. 5. the slice level is adjustable in 256 steps controlled by register limsl (d2h). 6. guaranteed by design. 7. the hysteresis is adjustable in 8 steps controlled by bits htlcb[2:0] of register limloscon (d1h). 8. reference frequency of 19.44 mhz, with a phase-noise of less than - 140 dbc for frequencies of more than 12 khz from the carrier (measured during 60 seconds, within the appropriate bandwidth). 9. for bit rates lower than 1.8 gbit/s, the jitter decreases by the octave division ratio m. table 60 default test settings pin setting ui = low pre-programmed mode dr0 = low, dr1 = high, dr2 = low stm16/oc48 lm0 = high, lm1 = high, lm2 = high normal mode enrx = high receiver enabled entx = high transmitter enabled enddr = low ddr mode disabled lowswing = high low lvds swing fref0 = high, fref1 = high 19.44 mhz reference rref r rref =10k w to v ee ipump open circuit rssi open circuit losth v losth = 0.6 v entxsc = high serial output clock enabled winsize = high 1000 ppm enba = high automatic byte alignment pareven = high even parity cref(q) ac-coupled, f i = 19.44 mhz, v i = 0.2 v (p-p) single-ended rxsd(q) input stm16; prbs (2 23 - 1) rxpd0(q) to rxpd3(q), rxfp(q), rxpar(q), rxpc(q), txpco(q), txparerr(q), txprscl(q) and rxprscl(q) 100 w differential outputs txpc(q), txpd0(q) to txpd3(q) and txpar open circuit fiforeset = low normal mode clkdir = high co-directional clocking txsd(q) and txsc(q) external load of 50 w to v cc cmos outputs not loaded
2003 dec 16 56 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw handbook, full pagewidth mgx390 t d-c txsc txsd the timing is measured from the crossover point of the clock output signal to the crossover point of the data output (all signa ls are differential). fig.27 serial bus output timing. handbook, full pagewidth mgx478 rxpc rxpd0 to rxpd3 rxfp, rxpar t d-c the timing is measured from the crossover point of the clock output signal to the crossover point of the data output (all signa ls are differential). fig.28 parallel bus output timing. handbook, full pagewidth mce422 txpd0 to txpd3 txpco, txpc t h t su valid data t clk fig.29 parallel bus co-directional (txpc) and contra-directional (txpco) timing. the timing is measured from the crossover point of the reference signal to the crossover point of the input.
2003 dec 16 57 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw application information calculations on the clean-up pll the important specifications of the clean-up pll are the bandwidth (f - 3db ) and the jitter peaking. if these are known, the component parameters can be calculated. first assume that the bandwidth of the vcxo control input (f - 3db(vcxo) ) is much higher than f - 3db and c2 is left out. this simplifies the loop into a second order, type ii pll. in a second order pll, the damping factor z determines the amount of peaking. to obtain peaking of less than 0.1 db, z must be higher than 4.3. for peaking of less than 0.05 db, z must be higher than 6. see fig.30 for an example. now r and c1 may be calculated with the following formulas: where: rdiv = reference divider ratio (1, 2, 4, 8, 16 or 32) f - 3db = clean-up pll bandwidth in hz k vcxo = vcxo gain in hz/v i cp = charge pump current in a (100 m a or 1 ma, depending on i 2 c-bus bit cluppllhg) z = damping factor. these formulas are valid if: z >> 1 and f - 3db(vcxo) >2 f - 3db and . the transfer has a first order roll-off (i.e. 20 db/decade), up to the bandwidth of the vcxo control input. if a second order roll-off is required c2 may be added, as long as example: the clean-up pll uses a vcxo with a frequency of 20 mhz and has a gain k vcxo = 2000 hz/v. the bandwidth of the control input is f - 3db(vcxo) = 10 khz. since the reference frequency is 20 mhz, the reference divider ratio rdiv = 1. according to the specification, the maximum allowed jitter peaking is 0.1 db. to add some margin the design is for less than 0.05 db peaking, so z = 6. also according to the specification, f - 3db should be less than 100 khz. to satisfy the conditions as previously described, f - 3db < 0.5 f - 3 db(vcxo) < 5 khz. to cope with component tolerances, f - 3db(vcxo) = 2.5 khz is chosen. choosing i cp = 1 ma yields r = 7854 w and c1 = 1.167 m f. to calculate f -3db and z , if r and c1 are known, use the following formulas: r rdiv 2 p f 3db C k vcxo i cp ----------------------------------------------------- - = c 1 k vcxo i cp z 2 rdiv p 2 f 3db C () 2 ------------------------------------------------------ = c1 c2 + 2 p r c1 c2 --------------------------------------------------- - 2f 3db C > c1 c2 + 2 p c1 c2 ----------------------------------------- 2f 3db C > r 12 p 2500 2000 100 10 6 C ----------------------------------------------- w 78540 w == c 1 2000 100 m f 6 2 1 p 2 2500 2 ------------------------------------------------- - 116.7nf == f 3db C k vcxo i cp r 2 p rdiv ------------------------------------------ - = z r 2 --- - k vcxo i cp c1 rdiv ---------------------------------------------- - =
2003 dec 16 58 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw handbook, full pagewidth 20 db/decade jitter peaking 40 db/decade mce423 f - 3 db (vcxo) f - 3 db log(f) [hz] j transfer [db] - 3 fig.30 clean-up pll jitter transfer. i/o configurations handbook, full pagewidth mdb068 v cc v bias out transmission lines to high- impedance input 50 w 50 w 50 w 50 w 50 w 50 w outq i swing in swing control on-chip off-chip fig.31 serial rf output (ac-coupled).
2003 dec 16 59 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw handbook, full pagewidth mdb069 v cc out transmission lines to high- impedance input 50 w 50 w 50 w 50 w 50 w 50 w outq i swing in swing control on-chip off-chip fig.32 serial rf output (dc-coupled). handbook, halfpage mgx391 50 w 300 w 50 w d dq 1.8 pf v ccd v ee 30 k w 30 k w fig.33 lvds input.
2003 dec 16 60 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw handbook, full pagewidth mgx392 v ref transmission lines to high- impedance input 50 w 50 w 100 w v cc out outq common mode control swing-setting in on-chip off-chip fig.34 lvds output (dc-coupled). handbook, full pagewidth mgx393 v ref v bias transmission lines ac coupling to high- impedance input 50 w 50 w 50 w 50 w v cc out outq common mode control swing-setting in on-chip off-chip fig.35 lvds output (ac-coupled).
2003 dec 16 61 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw 001aaa056 v ee v cc cref crefq 50 w 50 w fig.36 reference clock input.
2003 dec 16 62 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw package outline unit a max. a 1 a 2 a 3 b p h d h e l p z d (1) z e (1) cely w v q references outline version european projection issue date iec jedec jeita mm 1.2 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.15 15.85 1.15 0.85 7 0 0.08 0.08 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot638-1 01-03-30 03-04-07 d (1) e (1) 14.1 13.9 16.15 15.85 d h e h 7.1 6.1 7.1 6.1 1.15 0.85 b p b p e q e a 1 a l p detail x l (a 3 ) b 25 h d h e a 2 v m b d z d a c z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 10 mm scale htqfp100: plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad sot638-1 d h e h exposed die pad side
2003 dec 16 63 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson-t and ssop-t packages C for packages with a thickness 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2003 dec 16 64 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the reflow oven. the package body peak temperature must be kept as low as possible. 4. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 6. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on flex foil. however, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. the appropriate soldering profile can be provided on request. 9. hot bar or manual soldering is suitable for pmfp packages. additional soldering information the die pad has to be soldered to the pcb for thermal and grounding reasons. package (1) soldering method wave reflow (2) bga, htsson..t (3) , lbga, lfbga, sqfp, ssop..t (3) , tfbga, uson, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable (4) suitable plcc (5) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (5)(6) suitable ssop, tssop, vso, vssop not recommended (7) suitable cwqccn..l (8) , pmfp (9) , wqccn..l (8) not suitable not suitable
2003 dec 16 65 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2003 dec 16 66 philips semiconductors preliminary speci?cation 30 mbit/s to 3.2 gbit/s a-rate ? 4-bit ?bre optic transceiver tza3015hw purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands r56/04/pp 67 date of release: 2003 dec 16 document order number: 9397 750 12216

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